1. Technical Field
The invention relates to semiconductor devices and methods of forming the same, and more particularly, to semiconductor devices having a trench in a side portion of a conducting line pattern and methods of forming the same.
2. Discussion of the Related Art
A semiconductor fabrication process, in recent years, may employ a landing pad to accomplish high integration of a semiconductor device with a design rule below the submicron scale. The landing pad is formed to extend upward from an upper surface of a semiconductor substrate. The landing pad functions to electrically connect the discrete elements, which are located at different positions inside the semiconductor device. An insulating layer is typically provided between the landing pad and these elements adjacent to the landing pad. The discrete elements located on, or occupying the space around, the upper surface of a semiconductor substrate can be spaced farther from the semiconductor substrate because of the presence of the landing pad. Thus the area of the semiconductor substrate used for a semiconductor device is reduced.
The landing pad, however, due to shortcomings of the semiconductor fabrication process, may have structural problems that tend to cause electrical shorts between the landing pad and the adjacent discrete elements. These shortcomings generally result from fabricating with a reduced design rule. More specifically, this is because the landing pad has a small process margin for aligning discrete elements during the fabrication process.
Working towards a remedy, U.S. Pat. No. 6,335,237 to Sanh D. Tang et al. (the '237 patent) discloses a method of forming a capacitor and bitline structure.
According to the '237 patent, the method includes providing a semiconductor substrate having a plurality of electrical nodes. A stack of bitline materials are formed over at least a portion of the electrical nodes. Each of the bitline materials includes at least one conductive material and at least one insulative material, which are sequentially stacked. Then openings are formed in the electrical nodes through the bitline materials. Conductive masses are respectively formed in the openings. The conductive masses fill at least a portion of the openings.
However, this method has an increased risk of exposing the bitline materials through the openings during the semiconductor fabrication process. This reason for this risk is as follows. The conductive masses are insulated from the bitline materials using insulative spacers as an insulating layer. The insulative spacers are formed on sidewalls of the bitline materials, respectively. The insulative spacers are formed by using an etch process, which is performed on an overall surface of the semiconductor substrate. The etch process may show a non uniform etch rate at some portions of the semiconductor substrate. The insulative spacers may not fully cover the sidewalls of the bitline materials at the portions of the semiconductor substrate. Because of that, the bitline materials cause an electrical short with the conductive masses through the openings at the portions of the semiconductor substrate.